1. Field of the Invention
This invention relates to delay lines in general and, more particularly, logic gate based variable delay lines and variable frequency ring oscillators.
2. Description of the Prior Art
Delay lines are widely used in a variety of integrated circuit applications, such as delay-locked-loops and clock generators. The delay line is typically formed on an integrated circuit by cascading a string of logic inverters, each connection between the inverters serving as a "tap" along the delay line. The total delay through the delay line is approximately equal to the sum of the individual inverter propagation delays. One method of controlling the amount of delay through the line is by varying ("starving") the power supply current supplied to the inverters. Another way is by varying the amount of capacitance loading on the output of the inverters as shown in U.S. Pat. No. 5,012,142, assigned to the same assignee as this invention and incorporated herein by reference.
A drawback to the above delay control approaches is the possible inability of the delay line delay to be as short as the technology used to implement the delay line allows. For example, the minimum delay for a current "starved" inverter based delay line may be significantly longer than if the inverters were not current limited. Further, at maximum delay, the signals propagating through the inverters may be so slow in rise and fall times that instabilities in circuits coupled to the delay line may occur.
Connecting the input of an active delay line to its output forms a ring oscillator which are widely used in, for example, integrated circuit phase locked loops. The oscillators generally have an odd number of inverting delay stages (typically logic inverters) serially connected into a ring with the oscillation frequency being substantially determined by the inverter propagation of delays. The amount of delay by each inverter is controlled as discussed above. In correspondence with the variable delay line problems mentioned above, while the ring oscillator does allow for wide variations in oscillation frequency, the highest oscillation frequency may be considerably less than the maximum possible for the logic technology used to implement the oscillator. Further, the lowest frequency of oscillation may not have sufficient amplitude for circuits utilizing the output of the oscillator and the oscillator may completely stop oscillation due to the gain of the inverters being insufficient to support oscillation. Still further, the relationship between the control signal and the oscillation frequency may be very non-linear.
Thus, it is desirable to provide a variable delay line design having wide delay range without having too slow logic rise and fall times at the longest desired delays and having shorter minimum delays than prior art designs. Further, it is desirable to provide a ring oscillator design that has wide frequency variation range, a higher maximum oscillation frequency than prior art designs, and consistent, full amplitude, reliable oscillation at the lowest desired frequency of oscillation. In addition, it is desirable to provide an oscillator with an approximately linear control signal to oscillator frequency relationship.